1. Field of the Invention
This invention relates to a single-chip architecture for a shared-memory router.
2. Related Art
In a packet-switched network, a xe2x80x9crouterxe2x80x9d is a device which receives packets on one or more input interfaces and which outputs those packets on one of a plurality of output interfaces, so as to move those packets within the network from a source device to a destination device. Each packet includes header information which indicates the destination device (and other information), and the router includes routing information which associates an output interface with information about the destination device (possibly with other information). The router can also perform other operations on packets, such as rewriting the packets"" headers according to their routing protocol or to reencapsulate the packets from a first routing protocol to a second routing protocol.
It is advantageous for routers to operate as quickly as possible, so that as many packets as possible can be switched in a unit time. Because routers are nearly ubiquitous in packet-switched networks, it is also advantageous for routers to occupy as little space as possible and to be easily integrated into a networking system. For example, implementing a router on a single chip (that is, a single integrated circuit) would be particularly advantageous.
In this regard, one problem which has arisen in the art is that individual integrated circuits and their packages are relatively limited in resources needed to implement a router. In particular, individual chips have only a relatively limited number of pins, a relatively limited die area, and a relatively limited amount of power available for operation. These limitations severely limit the possibility of providing a useful router on a single chip. Routing devices generally need relatively more input and output ports (thus requiring relatively more pins), relatively more lookup table space (thus requiring relatively larger die size for memory), relatively more packet buffering space (thus requiring relatively larger die size for memory), and relatively more packets routed in unit time (thus requiring relatively larger die size for processing ability and relatively larger power dissipation for speed).
Accordingly, it would be advantageous to provide a single-chip router. This advantage is achieved in an embodiment of the invention in which a router integrated on a single chip shares memory among packet buffers for receiving packets, packet buffers for transmitting packets, and packet header buffers for packet forwarding lookup, and in which accesses to that shared memory are multiplexed and prioritized to maximize throughput and minimize routing latency.
The invention provides a single-chip router. The router includes a memory shared among packet buffers for receiving packets, packet buffers for transmitting packets, and packet header buffers for packet forwarding lookup. Accesses to that shared memory are multiplexed and prioritized. Packet reception is performed with relatively high priority, packet transmission is performed with medium priority, and packet forwarding lookup is performed with relatively low priority.
In a preferred embodiment, the single-chip router includes circuits for serially receiving packet header information, converting that information into a parallel format for transmission to an SRAM for lookup, and queuing input packets for later forwarding at an output port. Similarly, in a preferred embodiment, the single-chip router includes circuits for queuing output packets for transmission at an output port, receiving packet forwarding information from the SRAM in a parallel format, and converting packet header information from output packets into a serial format for transmission. The single-chip router also includes a region in its shared memory for a packet forwarding table, and circuits for performing forwarding lookup responsive to packet header information.